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preliminary data sheet july 2000 LU3X31T-T64 single-port 3 v 10/100 ethernet transceiver tx overview the LU3X31T-T64 is a fully integrated 10/100 mbits/s physical layer device with an inte- grated transceiver. it is provided in a 64-pin tqfp package with low-power operation and powerdown modes. typical applications for this part are cardbus and pcmcia ethernet products. operating at 3.3 v, the LU3X31T-T64 is a powerful device for the forward migration of legacy 10 mbits/s products and noncom- pliant (does not have autonegotiation) 100 mbits/s devices. the LU3X31T-T64 was designed from the beginning to conform fully with all pertinent specifica- tions, from the iso * /iec 11801 and eia ? /tia 568 cabling guidelines to ansi ? x3.263 tp-pmd to ieee 802.3 ethernet specifications. features n single-chip integrated physical layer and trans- ceiver for 10base-t and/or 100base-t functions n ieee 802.3 compatible 10base-t and 100base-t physical layer interface and ansi x3.263 tp-pmd compatible transceiver n built-in analog 10 mbits/s receive filter, eliminating the need for external filters n built-in 10 mbits/s transmit filter n 10 mbits/s pll exceeding tolerances for both pre- amble and data jitter n 100 mbits/s pll, combined with the digital adap- tive equalizer, robustly handles variations in rise- fall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline wander n transmit rise-fall time can be manipulated to pro- vide lower emissions, amplitude fully compatible for proper interoperability n programmable scrambler seed for better fcc compliancy n ieee 802.3u clause 28 compliant autonegotiation for full 10 mbits/s and 100 mbits/s control n fully configurable via pins and management accesses n extended management support with interrupt capabilities n phy mib support n symbol mode option n low-power operation: <150 ma max n low autonegotiation power: <30 ma n very low powerdown mode: <5 ma n 64-pin tqfp package (10 mm x 10 mm x 1.4 mm) * iso is a registered trademark of the international organization for standardization. ? eia is a registered trademark of the electronic industries asso- ciation. ? ansi is a registered trademark of the american national stan- dards institute, inc. ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
table of contents contents page LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 2 lucent technologies inc. overview....................................................................................................................... ............................................ 1 features ....................................................................................................................... ............................................ 1 pin descriptions............................................................................................................... ......................................... 6 functional description ......................................................................................................... ................................... 10 media independent interface (mii) .............................................................................................. ........................ 10 100base-x module............................................................................................................... ............................... 11 100base-x receiver ............................................................................................................. .............................. 14 100base-x link monitor ......................................................................................................... ............................. 15 100base-tx transceiver......................................................................................................... ............................ 16 10base-t module ................................................................................................................ ................................ 16 clock synthesizer.............................................................................................................. .................................. 18 autonegotiation ................................................................................................................ ................................... 18 reset operation ................................................................................................................ .................................. 19 100base-x pcs configuration.................................................................................................... ........................ 20 mii registers .................................................................................................................. ........................................ 21 dc and ac specifications....................................................................................................... .................................. 31 absolute maximum ratings....................................................................................................... .......................... 31 clock timing................................................................................................................... ........................................ 32 outline diagram................................................................................................................ ...................................... 43 64-pin tqfp .................................................................................................................... ................................... 43 ordering information........................................................................................................... .................................... 44 ta bl es page table 1. twisted-pair magnetic interface ...................................................................................... ........................... 5 table 2. twisted-pair transceiver control ..................................................................................... ........................... 6 table 3. mii interface ........................................................................................................ ....................................... 6 table 4. phy address configuration ............................................................................................ ........................... 7 table 5. 100base-x pcs configuration.......................................................................................... ......................... 7 table 6. autonegotiation configuration ........................................................................................ ............................ 7 table 7. led and status outputs ............................................................................................... ............................. 8 table 8. clock and chip reset ................................................................................................. ............................... 9 table 9. power and ground ..................................................................................................... ................................ 9 table 10. symbol code scrambler ............................................................................................... ......................... 13 table 11. autonegotiation ..................................................................................................... ................................. 20 table 12. mii management registers ............................................................................................ ........................ 20 table 13. control register (register 0h) ...................................................................................... ......................... 21 table 14. status register (register 1h)....................................................................................... .......................... 23 table 15. phy identifier (register 2h) ........................................................................................ ........................... 25 table 16. phy identifier (register 3h) ........................................................................................ ........................... 25 table 17. autonegotiation advertisement (register 4h) ......................................................................... ............... 25 table 18. autonegotiation link partner ability (register 5h) .................................................................. ............... 25 table 19. autonegotiation expansion register (register 6h) .................................................................... ............ 26 table 20. receive error counter (register 15h)................................................................................ .................... 26 table 21. phy control/status register (register 17h).......................................................................... ................ 27 table 22. config 100 register (register 18h).................................................................................. ...................... 28 table 23. phy address register (register 19h) ................................................................................. .................. 29 table 24. config 10 register (register 1ah) ................................................................................... ...................... 29 table 25. status 100 register (register 1bh) .................................................................................. ..................... 30 table 26. status 10 register (register 1ch) ................................................................................... ...................... 30
table of contents (continued) tables (continued) page preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx lucent technologies inc. 3 table 27. interrupt mask register (register 1dh).............................................................................. .................... 30 table 28. interrupt status register (register 1eh) ............................................................................ .................... 31 table 29. absolute maximum ratings............................................................................................ ........................ 31 table 30. operating conditions................................................................................................ .............................. 31 table 31. dc characteristics.................................................................................................. ................................. 32 table 32. system clock (xin) .................................................................................................. ............................... 32 table 33. transmit clock (input and output) ................................................................................... ....................... 33 table 34. management clock.................................................................................................... ............................. 34 table 35. mii receive timing.................................................................................................. ............................... 35 table 36. mii transmit timing ................................................................................................. ............................... 36 table 37. transmit timing ..................................................................................................... ................................. 37 table 38. receive timing...................................................................................................... ................................. 38 table 39. reset and configuration timing ...................................................................................... ....................... 39 table 40. pmd characteristics................................................................................................. .............................. 40 figures page figure 1. LU3X31T-T64 block diagram ........................................................................................... ........................ 4 figure 2. pin diagram ......................................................................................................... ..................................... 5 figure 3. 100base-x data path ................................................................................................. ............................ 12 figure 4. 10base-t module data path ........................................................................................... ....................... 16 figure 5. hardware reset configurations....................................................................................... ....................... 19 figure 6. system timing....................................................................................................... ................................. 32 figure 7. transmit timing (input and output) .................................................................................. ...................... 33 figure 8. management timing ................................................................................................... ............................ 34 figure 9. mii receive timing .................................................................................................. ............................... 35 figure 10. mii transmit timing ................................................................................................ .............................. 36 figure 11. transmit timing .................................................................................................... ................................ 37 figure 12. receive timing ..................................................................................................... ................................ 38 figure 13. reset and configuration timing ..................................................................................... ...................... 39 figure 14. pmd timing ......................................................................................................... ................................. 40 figure 15. connection diagrams (frequency references)......................................................................... ........... 41 figure 16. connection diagrams (10/100btx operation) .......................................................................... ........... 42
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 4 lucent technologies inc. features (continued) 5-6779(f).ar.2 figure 1. LU3X31T-T64 block diagram mii interface logic led s led s management interface register/ config/ control 10/100-rx pcs 10/100-tx pcs 10/100-tx drivers autoneg rx10 squelch clock synthesis and recovery adaptive equalizer baseline wander correction mdio mdc txd txen txer txclk rxd rxdv rxer rxclk col crs mdiointz tptx tprx
lucent technologies inc. 5 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx features (continued) 5-6780(f).br.5 figure 2. pin diagram table 1. twisted-pair magnetic interface pin no. pin name i/o pin description 53 54 tptx+ tptxC o twisted-pair transmit driver pair. these pins are used to transmit 100base-t mlt-3 signals on category 5 utp cable or 10base-t manchester signals on category 3 utp cable. 61 62 tprx+ tprxC i twisted-pair receive pair. these pins receive 100base-t mlt 3 or 10base-t manchester data. 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 txd0 txd1 txd2 txd3 txer txen gnd8 v dd 8 rxclk rxd0 rxd1 rxd2 rxd3 rxer rxdv ledsp/10fden xout xin xtlv dd mdc lnkled/bpalign ledfd/10hden ledcol/bp4b5b ledtx/actled/bpscr ledrx col/phy[4] v dd 6 v dd 4 gnd4 mdio crs/phy[3] txclk ref10 txv dd 1 txgnd1 tptx+ tptxC txv dd 2 csgnd csv dd csv dd rxv dd 1 rxgnd1 tprx+ tprxC rxgnd2 rxv dd 2 resv 100fden gnd9 autonen tptxtr eqgnd1 eqv dd 1 resv rstz phy[0] gnd1 v dd 1 mdiointz/phy[2] 100hden v dd 5 12 phy[1] 48 47 46 45 44 43 42 41 40 39 38 36 35 34 33 37 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ref100
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 6 lucent technologies inc. pin descriptions table 2. twisted-pair transceiver control table 3. mii interface note: smaller font indicates that the pin has multiple functions. pin no. pin name i/o pin description 50 ref100 i reference resistor for 100 mbits/s twisted-pair driver. connect this pin to ground through a 301 w resistor. 49 ref10 i reference resistor for 10 mbits/s twisted-pair driver. connect this pin to ground through a 4.64 k w resistor. 5tptxtr i twisted-pair transmitter 3-state. a high on this pin will 3-state the twisted-pair outputs. tie to ground in normal operation. pin no. pin name i/o pin description 18 rxdv o receive data valid. signals the presence of data on rxd[3:0]. 19 rxer o receive error. indicates a received coding error has occurred. 20 rxd3 o receive data[3]. 21 rxd2 o receive data[2]. 22 rxd1 o receive data[1]. 23 rxd0 o receive data[0]. 24 rxclk o receive clock. 27 txen i transmit enable. signals the presence of data on txd[3:0]. 28 txer i transmit error. indicates a transmit coding error has occurred. 29 txd3 i transmit data[3]. 30 txd2 i transmit data[2]. 31 txd1 i transmit data[1]. 32 txd0 i transmit data[0]. 33 txclk o transmit clock. 34 crs/ phy[3] i/o carrier sense/phy address[3]. this output pin indicates the carrier sense condition. see table 4 for phy[3] description. 39 col/ phy[4] i/o collision/false carrier sense. this output pin indicates collision condition in normal mii operation and is squelch jabber in 10 mbits/s mode. see table 4 for phy[4] description. 35 mdio i/o management data i/o. serial access to device config registers. 45 mdc i management data clock. clock for r/w of device config registers. 16 mdiointz/ phy[2] i/o mdio interrupt (active-low). the mdio interrupt pin outputs a logic 0 pulse of 40 ns, synchronous to xin, whenever an unmasked inter- rupt condition is detected. refer to management registers 1dh and 1eh for interrupt conditions. see table 4 for phy[2] description.
lucent technologies inc. 7 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx pin descriptions (continued) table 4. phy address configuration note: smaller font indicates that the pin has multiple functions. table 5. 100base-x pcs configuration note: smaller font indicates that the pin has multiple functions. table 6. autonegotiation configuration (refer to table 11.) pin no. pin name i/o pin description 10 12 16 34 39 phy[0] phy[1] phy[2]/ mdiointz phy[3]/ crs phy[4]/ col i i i/o i/o i/o phy address[4:0]. these 5 pins are detected during powerup or reset to initialize the phy address used for mii management register interface. phy address 00h forces the phy into mii isolate mode. phy address pins[4:2] have an internal 40 k w pull-down resistor. see table 3 for mdiointz, crs, and col description. pin no. pin name i/o pin description 41 bpscr/ ledtx / actled i/o bypass scrambler mode. a high value on this pin during powerup or reset will bypass the scramble/descramble operations in 100base-x data path. this pin has an internal 40 k w pull-down resistor. see table 7 for ledtx/ actled description. 42 bp4b5b/ ledcol i/o bypass 4b/5b mode. a high value on this pin during powerup or reset will bypass the 4b/5b encoder of the phy. this pin has an internal 40 k w pull- down resistor. see table 7 for ledcol description. 44 bpalign/ lnkled i/o bypass alignment mode. a high value on this pin during powerup or reset will bypass the alignment feature of the phy. this bypass mode provides a symbol interface. this pin has an internal 40 k w pull-down. see table 7 for lnkled description. pin no. pin name i/o pin description 4autonen i autonegotiation enable. a high value on this pin during powerup or reset will enable autonegotiation; a low value will disable it. 2 100fden i 100 full-duplex enable. the logic level of this pin is detected at powerup or reset to determine whether 100 mbits/s full-duplex mode is available. when autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonegotiation is not enabled, this input will select the mode of operation. 11 100hden i 100 half-duplex enable. the logic level of this pin is detected at powerup or reset to determine whether 100 mbits/s half-duplex mode is available. when autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonegotiation is not enabled, this input will select the mode of operation. 17 10fden/ ledsp i/o 10 full-duplex enable. the logic level of this pin is detected at powerup or reset to determine whether 10 mbits/s full-duplex mode is avail- able. when autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonegotiation is not enabled, this input will select the mode of operation. this pin has an internal 40 k w pull-up resistor. see table 7 for ledsp description. note: smaller font indicates that the pin has multiple functions.
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 8 lucent technologies inc. note: smaller font indicates that the pin has multiple functions. table 7. led and status outputs note: smaller font indicates that the pin has multiple functions. 43 10hden/ ledfd i/o 10 half-duplex enable. the logic level of this pin is detected at powerup or reset to determine whether 10 mbits/s half-duplex mode is available. when autonegotiation is enabled, this input sets the ability register bit in advertise- ment register 4. when autonegotiation is not enabled, this input will select the mode of operation. this pin has an internal 40 k w pull-up resistor. see table 7 for ledfd description. pin no. pin name i/o pin description 40 ledrx i/o receive led. this output will drive a 10 ma led if the LU3X31T-T64 is receiving data from the utp cable. this pin has an internal 40 k w pull-down resistor. the led should be connected as logic 0 configuration as shown in figure 5, without the 10 k w resistor. 41 ledtx/actled/ bpscr i/o transmit led or activity led. when bit 7 of register 17h is 0, this output will drive a 10 ma led if the LU3X31T-T64 is transmitting data. if the control bit is set, then the led will be driven whenever receive or transmit activity is present. this pin has an internal 40 k w pull-down. the led should be con- nected as logic 0 configuration in figure 5 without the 10 k w resistor. see table 5 for bpscr description. 44 lnkled/ bpalign i/o link led. this output will drive a 10 ma led for as long as a valid link exists across the cable. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., bypass align mode as shown in figure 5. see table 5 for bpalign description. 42 ledcol/ bp4b5b i/o collision led. this output will drive a 10 ma led whenever the lu3x31t- t64 senses a collision has occurred. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., bypass 4b/5b mode as shown in fig- ure 5. see table 5 for bp4b5b description. 43 ledfd/ 10hden i/o full-duplex status. this output will drive a 10 ma led when the lu3x31t- t64 is in full-duplex mode. place a 10 k w resistor across the led pins if set- ting to nondefault mode, i.e., 10hd disable mode as shown in figure 5. see table 6 for 10hden description. 17 ledsp/ 10fden i/o speed status. this output will drive a 10 ma led when the LU3X31T-T64 is in 100 mbits/s mode. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., 10fd disable mode as shown in figure 5. see table 6 for 10fden description. pin no. pin name i/o pin description pin descriptions (continued) table 6. autonegotiation configuration (refer to table 11.) (continued)
lucent technologies inc. 9 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx pin descriptions (continued) table 8. clock and chip reset table 9. power and ground pin no. pin name i/o pin description 47 xin i crystal oscillator input or clock input. see figure 15 for a con- nection diagram. 48 xout o crystal oscillator feedback output. if a single-ended external clock is connected to xin pin, then xout should be grounded for minimum power consumption. see figure 15 for a connection dia- gram. 9rstz i reset (active-low). this input must be held low for a minimum of 1 ms to reset the LU3X31T-T64. 1 8 resv reserved. these pins are unused inputs and should be tied to ground. plane v cc pin associated ground pin name pin number name pin number rx analog rxv dd 1 rxv dd 2 59 64 rxgnd1 rxgnd2 60 63 tx analog txv dd 1 txv dd 2 51 55 txgnd1 52 cs csv dd csv dd 57 58 csgnd 56 digital v dd 1 v dd 4 v dd 5 v dd 6 v dd 8 eqv dd 1 15 37 13 38 25 7 gnd1 gnd4 gnd8 gnd9 eqgnd1 14 36 26 3 6 clock xtlv dd 46
10 lucent technologies inc. LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 functional description the LU3X31T-T64 integrates a 100base-x physical sublayer (phy), a 100base-tx physical medium dependent (pmd) transceiver, and a complete 10base- t module into a single chip for both 10 mbits/s and 100 mbits/s ethernet operation. this device provides an ieee 802.3u compliant media independent interface (mii) to communicate between the physical signaling and the medium access control (mac) layers for both 100base-x and 10base-t operations. the device is capable of operating in either full-duplex mode or half- duplex mode in either 10 mbits/s or 100 mbits/s opera- tion. operational modes can be selected by hardware configuration pins, selected by software settings of management registers, or determined by the on-chip autonegotiation logic. the 10base-t section of the device consists of the 10 mbits/s transceiver module with filters and a manchester endec module. the 100base-x section of the device implements the following functional blocks: n 100base-x physical coding sublayer (pcs) n 100base-x physical medium attachment (pma) n twisted-pair transceiver the 100base-x and 10base-t sections share the fol- lowing functional blocks: n clock synthesizer module (csm) n mii registers n ieee 802.3u autonegotiation each of these functional blocks is described below. media independent interface (mii) the LU3X31T-T64 implements an ieee 802.3u clause 22 compliant mii as described below. interface signals transmit data interface. the mii transmit data inter- face comprises seven signals: txd[3:0] are the nibble size data path, txen signals the presence of data on txd, txer indicates that a transmit coding error has occurred, and txclk is the transmit clock that syn- chronizes all the transmit signals. txclk is supplied by the on-chip clock synthesizer. receive data interface. the mii receive data interface comprises seven signals: rxd[3:0] are the nibble size data path, rxdv signals the presence of data on rxd, rxer indicates a received coding error, and rxclk is the receive clock. depending upon the operation mode, rxclk is generated by the clock recovery module of either the 100base-x or 10base-t receiver. status interface. two status signals, col and crs, are generated in the LU3X31T-T64 to indicate collision status and carrier sense status to the mac. col is asserted asynchronously whenever LU3X31T-T64 is transmitting and receiving at the same time in a half- duplex operation mode. in the full-duplex mode, col is inactive. crs is asserted asynchronously whenever there is activity on either the transmitter or the receiver. in full-duplex mode, crs is asserted only when there is activity on the receiver. operation modes the LU3X31T-T64 supports three operation modes and an isolate mode as described below. 100 mbits/s mode. for 100 mbits/s operation, the mii operates in nibble mode with a clock rate of 25 mhz. in normal operation, the mii data at rxd[3:0] and txd[3:0] are 4 bits wide. in bypass mode (either byp_4b5b or byp_align option selected), the mii data takes the form of 5-bit code-groups. the least sig- nificant 4 bits appear on txd[3:0] and rxd[3:0] as usual, and the most significant bits (txd[4] and rxd[4]) appear on the txer and rxer pins, respec- tively. 10 mbits/s mode. for 10 mbits/s operation, the txclk and rxclk operate at 2.5 mhz. the data paths are always 4 bits wide using txd[3:0] and rxd[3:0] signal lines.
lucent technologies inc. 11 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx functional description (continued) mii isolate mode. the LU3X31T-T64 implements an mii isolate mode that is controlled by bit 10 of the con- trol register (register 0h). the LU3X31T-T64 will set this bit to one if the phy address is set to 00000 upon pow- erup/hardware reset. otherwise, the LU3X31T-T64 will initialize this bit to 0. setting this bit to a 1 will put the LU3X31T-T64 into isolate mode. the isolate mode can also be activated by setting the phy address (bits 15 through 11 of register 19h) to 0 through the serial management interface, although the content of the isolate register is not affected by the modification of phy address. the LU3X31T-T64 does not respond to packet data present at txd[3:0], txen, and txer inputs and pre- sents a high impedance on the txclk, rxclk, rxdv, rxer, rxd[3:0], col, and crs outputs. the LU3X31T-T64 will continue to respond to all manage- ment transactions. serial management interface the serial management interface (smi) is the part of the mii that is used to control and monitor status of the LU3X31T-T64. this mechanism corresponds to the mii specification for 100base-x (clause 22) and supports registers 0 through 6. additional vendor-specific regis- ters are implemented within the range of 16 to 31. all the registers are described in mii registers on page 21 of this data sheet. management register access. the smi consists of two pins, management data clock (mdc) and manage- ment data input/output (mdio). the LU3X31T-T64 is designed to support an mdc frequency ranging up to the ieee specification of 2.5 mhz. the mdio line is bi- directional and may be shared by up to 32 devices. the mdio pin requires a 1.5 k w pull-up resistor which, during idle and turnaround periods, will pull mdio to a logic 1 state. each mii management data frame is 64 bits long. the first 32 bits are preamble consisting of 32 contiguous logic 1 bits on mdio and 32 correspond- ing cycles on mdc. following preamble is the start-of- frame field indicated by a <01> pattern. the next field signals the operation code (op): <10> indicates read from mii management register operation, and <01> indicates write to mii management register opera- tion. the next two fields are phy device address and mii management register address. both of them are 5 bits wide, and the most significant bit is transferred first. during read operation, a 2-bit turnaround (ta) time spacing between register address field and data field is provided for the mdio to avoid contention. following the turnaround time, a 16-bit data stream is read from or written into the mii management registers of the LU3X31T-T64. the LU3X31T-T64 supports a preamble suppression mode as indicated by a 1 in bit 6 of the basic mode sta- tus register (bmsr, address 01h). if the station man- agement entity (i.e., mac or other management controller) determines that all phys in the system sup- port preamble suppression by returning a 1 in this bit, then the station management entity need not generate preamble for each management transaction. the LU3X31T-T64 requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. this requirement is generally met by the manda- tory pull-up resistor on mdio or the management access made to determine whether preamble suppres- sion is supported. while the LU3X31T-T64 will respond to management accesses without preamble, a mini- mum of one idle bit between management transactions is required as specified in ieee 802.3u. the phy device address for LU3X31T-T64 is stored in the phy address register (register address 19h). it is initialized by the five i/o pins designated as phy[4:0] during powerup or hardware reset and can be changed afterward by writing into register address 19h. mdio interrupt. the LU3X31T-T64 implements inter- rupt capability that can be used to notify the manage- ment station of certain events. it generates an active- high interrupt signal on the mdiointz output pin whenever one of the interrupt status registers (register address 1eh) becomes set while its corresponding interrupt mask register (register address 1dh) is unmasked. reading the interrupt status register (regis- ter 1eh) shows the source of the interrupt and clears the interrupt output signal. in addition to the mdiointz pin, the LU3X31T-T64 can also support the interrupt scheme used by the ti thun- derlan * mac. this option can be enabled by setting bit 11 of register 17h. whenever this bit is set, the inter- rupt is signaled through both the mdiointz pin and embedded in the mdio signal. 100base-x module the LU3X31T-T64 implements a 100base-x compliant pcs and pma and 100base-tx compliant tp-pmd as illustrated in figure 3. bypass options for each of the major functional blocks within the 100base-x pcs pro- vides flexibility for various applications. 100 mbits/s phy loopback is included for diagnostic purposes. * ti is a registered trademark and thunderlan is a trademark of texas instruments, inc.
12 lucent technologies inc. LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 functional description (continued) 5-6781(f).ar.2 figure 3. 100base-x data path equalizer clock recovery serial to parallel de- scrambler 5b/4b decode receive state machine transmit state machine 4b/5b encode scrambler parallel to serial mlt-3 state machine 10/100 transmit driver tprx tptx 100 mbit phy loopback path byp-scr byp-4b5b byp-align rxclk rxd[3:0] crs rxdv rxer 100base-x receiver 100base-x transmitter col txclk txen txer txd[3:0] byp-4b5b byp-scr byp-align 100base-x transmitter the 100base-x transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as provided by the mii, to a 125 mbits/s serial data stream. the LU3X31T-T64 implements the 100base-x transmit state machine as specified in the ieee 802.3u standard, clause 24 and comprises the following func- tional blocks in its data path: n symbol encoder n scrambler block n parallel/serial converter and nrz/nrzi encoder block symbol encoder. the symbol encoder converts 4-bit (4b) nibble data generated by the mac into 5-bit (5b) symbols for transmission. this conversion is required to allow control symbols to be combined with data symbols. refer to the table below for 4b to 5b symbol mapping. following onset of the txen signal, the 4b/5b symbol encoder replaces the first two nibbles of the preamble from the mac frame with a /j/k code-group pair (11000 10001) start-of-stream delimiter (ssd). the symbol encoder then replaces subsequent 4b codes with cor- responding 5b symbols. following negation of the txen signal, the encoder substitutes the first two idle symbols with a /t/r code-group pair (01101 00111) end-of-stream delimiter (esd) and then continuously injects idle symbols into the transmit data stream until the next transmit packet is detected.
lucent technologies inc. 13 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx functional description (continued) assertion of the txer input while the txen input is also asserted will cause the LU3X31T-T64 to substitute halt code-groups for the 5b code derived from data present at txd[3:0]. however, the ssd (/j/k) and esd (/t/r) will not be substituted with halt code-groups. hence, the assertion of txer while txen is asserted will result in a frame properly encapsulated with the /j/ k and /t/r delimiters which contains halt code- groups in place of the data code-groups. the 100 mbits/s symbol decoder translates all invalid code groups into 0eh by default. in case the accept halt register is set (bit 5 of register 18h), the halt code-group (00100) is translated into 05h instead. table 10. symbol code scrambler symbol name 5b code [4:0] 4b code [3:0] interpretation 0 11110 0000 data 0 1 01001 0001 data 1 2 10100 0010 data 2 3 10101 0011 data 3 4 01010 0100 data 4 5 01011 0101 data 5 6 01110 0110 data 6 7 01111 0111 data 7 8 10010 1000 data 8 9 10011 1001 data 9 a 10110 1010 data a b 10111 1011 data b c 11010 1100 data c d 11011 1101 data d e 11100 1110 data e f 11101 1111 data f i 11111 undefined idle: interstream fill code j 11000 0101 first start-of-stream delimiter k 10001 0101 second start-of-stream delimiter t 01101 undefined first end-of-stream delimiter r 00111 undefined second end-of-stream delimiter h 00100 undefined halt: transfer error v 00000 undefined invalid code v 00001 undefined invalid code v 00010 undefined invalid code v 00011 undefined invalid code v 00101 undefined invalid code v 00110 undefined invalid code v 01000 undefined invalid code v 01100 undefined invalid code v 10000 undefined invalid code v 11001 undefined invalid code
14 lucent technologies inc. LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 functional description (continued) scrambler. for 100base-tx applications, the scram- bler is required to control the radiated emissions at the media connector and on the twisted-pair cable. the LU3X31T-T64 implements a data scrambler as defined by the tp-pmd stream cipher function. the scrambler uses an 11-bit ciphering linear feedback shift register (lfsr) with the following recursive linear func- tion: x[n] = x[n C 11] + x[n C 9] (modulo 2) the output of the lfsr is combined with the 5b data from the symbol encoder via an exclusive-or logic function. by scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. a seed value for the scrambler function can be loaded by setting bit 4 of register 18h. when this bit is set, the content of bits 10 though 0 of register 19h, which con- sists of the 5-bit phy address and a 6-bit user seed, will be loaded into the lfsr. by specifying unique seed value for each phy in a system, the total emi energy produced by a repeater application can be reduced. parallel-to-serial & nrz-to-nrzi conversion. after the transmit data stream is scrambled, the 5-bit code- group is loaded into a shift register and clocked out with a 125 mhz clock into a serial bit stream. the serialized data is further converted from nrz to nrzi format, which produces a transition on every logic 1 and no transition on logic 0. collision detect. during 100 mbits/s half-duplex oper- ation, a collision condition is indicated if the transmitter and receiver become active simultaneously. a collision condition is indicated by the col pin (pin 39). for full- duplex applications, the col signal is never asserted. a collision test register exists at address 0, bit 7. 100base-x receiver the 100base-x receiver consists of functional blocks required to recover and condition the 125 mbits/s receive data stream. the LU3X31T-T64 implements the 100base-x receive state machine diagram as given in ansi / ieee standard 802.3u, clause 24. the 125 mbits/s receive data stream originates from in a 100base-tx application. the receiver block consists of the following functional blocks: n clock recovery module n nrzi/nrz and serial/parallel decoder n descrambler n symbol alignment block n symbol decoder n collision detect block n carrier sense block n stream decoder block clock recovery. the clock recovery module accepts 125 mbits/s scrambled nrzi data stream from either the on-chip 100base-tx receiver or from an external 100base-fx transceiver. the LU3X31T-T64 uses an onboard digital phase-locked loop (pll) to extract clock information of the incoming nrzi data, which is then used to retime the data stream and set data bound- aries. after power-on or reset, the pll locks to a free-running 25 mhz clock derived from the external clock source. when initial lock is achieved, the pll switches to lock to the data stream, extracts a 125 mhz clock from the data, and uses it for bit framing of the recovered data. nrzi-to-nrz & serial-to-parallel conversion. the recovered data is converted from nrzi to nrz and then to a 5-bit parallel format for the LU3X31T-T64 descrambler. the 5-bit parallel data is not necessarily aligned to 4b/5b code-groups boundary. data descrambling. the scrambled data is presented in groups of 5 bits (quints) to a deciphering circuit that reverses the data scrambling process performed by the transmitter. the descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xored by the deciphering lfsr and descram- bled, again in groups of 5 bits (quints). in order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state moni- tor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the descrambler, the hold timer starts a 722 m s countdown.
lucent technologies inc. 15 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx functional description (continued) upon detection of sufficient idle symbols within the 722 m s period, the hold timer will reset and begin a new countdown. this monitoring operation will continue indefinitely given a properly operating network connec- tion with good signal integrity. if the link state monitor does not recognize sufficient unscrambled idle sym- bols within the 722 m s period, the entire descrambler will be forced out of the current state of synchronization and reset in order to reacquire synchronization. regis- ter 18h, bit 3, can be used to extend the timer to 2000 m s. symbol alignment. the symbol alignment circuit in the LU3X31T-T64 determines code word alignment by recognizing the /j/k delimiter pair. this circuit operates on unaligned 5-bit data from the descrambler and is capable of finding /j/k at any of the five possible start- ing positions within the descrambled data quints. once the /j/k symbol pair (11000 10001) is detected, subse- quent data is aligned on a fixed boundary. symbol decoding. the symbol decoder functions as a look-up table that translates incoming 5b symbols into 4b nibbles. the symbol decoder first detects the /j/k symbol pair preceded by idle symbols and replaces the symbol with mac preamble. all subse- quent 5b symbols are converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r sym- bol pair denoting the end of stream delimiter (esd). the translated data is presented on the rxd[3:0] sig- nal lines with rxd[0] representing the least significant bit of the translated nibble. valid data signal. the valid data signal (rxdv) indi- cates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv is asserted when the first nibble of translated /j/k is ready for transfer over the media independent interface (mii). it remains active until either the /t/r delimiter is recognized, link test indi- cates failure, or no signal is detected. on any of these conditions, rxdv is deasserted. receiver errors. the rxer signal is used to commu- nicate receiver error conditions. while the receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not map to a valid code-group. 100base-x link monitor the 100base-x link monitor function allows the receiver to ensure that reliable data is being received. without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. the LU3X31T-T64 performs the link integrity test as outlined in ieee 100base-x (clause 24) link monitor state diagram. the link status is multiplexed with the 10 mbits/s link status to form the reportable link status bit in serial management register 1. this status also drives the lnkled pin. when persistent signal energy is detected on the net- work, the logic moves into a link-ready state, after approximately 500 m s, and waits for an enable from the autonegotiation module. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should autonegotiation be dis- abled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. carrier sense. carrier sense (crs) for 100 mbits/s operation is asserted upon the detection of two non- contiguous zeros occurring within any 10-bit boundary of the receive data stream. the carrier sense function is independent of symbol alignment. for 100 mbits/s half-duplex operation, crs is asserted during either packet transmission or recep- tion. for 100 mbits/s full-duplex operation, crs is asserted only during packet reception. when the idle symbol pair is detected in the receive data stream, crs is deasserted. bad ssd detection. a bad start of stream delimiter (bad ssd) is an error condition that occurs in the 100base-x receiver if carrier is detected (crs asserted) and a valid /j/k set of code groups (ssd) is not received. if this condition is detected, then the LU3X31T-T64 will assert rxer and present rxd[3:0] = 1110 to the mii for the cycles that correspond to received 5b code- groups until at least two idle code groups are detected. once at least two idle code groups are detected, rxer and crs become deasserted.
16 16 lucent technologies inc. LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 functional description (continued) 100base-tx transceiver LU3X31T-T64 implements a tp-pmd compliant trans- ceiver for 100base-tx operation. the differential trans- mit driver is shared by the 10base-t and 100base-tx subsystems. this arrangement results in one device that uses the same external magnetics for both the 10base-t and the 100base-tx transmission with sim- ple rc component connections. the individually wave- shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmit output driver. transmit drivers the LU3X31T-T64 100base-tx transmit driver imple- ments mlt-3 translation and wave-shaping functions. the rise/fall time of the output signal is closely con- trolled to conform to the target range specified in the ansi tp-pmd standard. twisted-pair receiver for 100base-tx operation, the incoming signal is detected by the on-chip twisted-pair receiver that com- prises the differential line receiver, an adaptive equal- izer, and baseline wander compensation circuits. the LU3X31T-T64 uses an adaptive equalizer which changes filter frequency response in accordance with cable length. the cable length is estimated based on the incoming signal strength. the equalizer tunes itself automatically for any cable length to compensate for amplitude and phase distortions incurred from the cable. 10base-t module the 10base-t transceiver module is ieee 802.3 com- pliant. it includes the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. figure 4 provides an overview for the 10base-t module. the LU3X31T-T64 10base-t module is comprised of the following functional blocks: n manchester encoder and decoder n collision detector n link test function n transmit driver and receiver n serial and parallel interface n jabber and sqe test functions n polarity detection and correction 5-6782(f)r3 figure 4. 10base-t module data path filter receive 10base-t smart clock wave 10/100 filter squelch recovery receive pcs 10base-t transmit pcs transmit driver shaper rxclk crs rxd[3:0] col txen txer txd[3:0] txclk 10 mbit phy loopback path tprx tptx rxdv
lucent technologies inc. 17 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx functional description (continued) operation modes the LU3X31T-T64 10base-t module is capable of operating in either half-duplex mode or full-duplex mode. in half-duplex mode, the LU3X31T-T64 functions as an ieee 802.3 compliant transceiver with fully inte- grated filtering. the col pin signals collision, and the crs is asserted during transmit and receive. in full- duplex mode, the LU3X31T-T64 can simultaneously transmit and receive data. manchester encoder/decoder. data encoding and transmission begins when the transmit enable input (txen) goes high and continues as long as the trans- ceiver is in good link state. transmission ends when the transmit enable input goes low. the last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0. decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separates the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when no more midbit transitions are detected. within one and a half bit times after the last bit, carrier sense is deasserted. transmit driver and receiver. LU3X31T-T64 inte- grates all the required signal conditioning functions in its 10base-t block such that external filters are not required. only an isolation transformer and impedance matching resistors are needed for the 10base-t trans- mit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated properly. smart squelch. the smart squelch circuit is responsi- ble for determining when valid data is present on the differential receive. the LU3X31T-T64 implements an intelligent receive squelch on the tprx differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10base-t standard) to determine the validity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit, and any pulses not exceeding the squelch level (either positive or negative, depend- ing upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. finally, the signal must exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected. only after all of these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. once good data has been detected, the squelch levels are reduced to mini- mize the effect of noise causing premature end of packet detection. the receive squelch threshold level can be lowered for use in longer cable applications. this is achieved by setting bit 11 or register address 1ah. carrier sense. carrier sense (crs) is asserted due to receive activity once valid data is detected via the smart squelch function. for 10 mbits/s half-duplex operation, crs is asserted during either packet transmission or reception. for 10 mbits/s full-duplex operation, the crs is asserted only on receive activity. crs is deasserted following an end of packet. collision detection. for half-duplex operation, a 10base-t collision is detected when the receive and transmit channels are active simultaneously. collisions are reported by the col signal. if the endec is trans- mitting when a collision is detected, the col signal remains set for the duration of the collision. sqe test function. approximately 1 m s after the transmission of each packet, a signal quality error (sqe) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. sqe is reported as a pulse on the col signal. this function can be disabled by setting bit 12 of register 1ah. the sqe test function is disabled in full-duplex mode. jabber function. the jabber function monitors the LU3X31T-T64's output and disables the transmitter if it attempts to transmit a longer than legal-sized packet. if txen is high for greater than 24 ms, the 10base-t transmitter will be disabled and col will go high. once disabled by the jabber function, the transmitter stays disabled for the entire time that the txen signal is asserted. this signal has to be deasserted for approximately 256 ms (the unjab time) before the jab- ber function re-enables the transmit outputs and de- asserts col signal. the jabber function can be disabled by setting bit 10 of register 1ah.
18 lucent technologies inc. LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 functional description (continued) link test function. a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted-pair transmitter, receiver, and col- lision detection functions. the link pulse generator produces pulses as defined in the ieee 802.3 10base-t standard. each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. automatic link polarity detection. the lu3x31t- t64's 10base-t transceiver module incorporates an automatic link polarity detection circuit. the inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive receive packets are received with inverted end of packet pulses. if the input polarity is reversed, the error condi- tion will be automatically corrected and reported in bit 15 of register 1ch. the automatic link polarity detection function can be disabled by setting bit 3 of register 1ah. clock synthesizer the LU3X31T-T64 implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. the clock source can be a quartz crystal or a ttl level signal at 25 mhz 50 ppm, as shown in figure 15. autonegotiation the autonegotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest-performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate autonegotiation abilities between two devices at each end of a link segment. for further detail regarding autonegotiation, refer to clause 28 of the ieee 802.3u specification. the LU3X31T-T64 supports four different ethernet protocols, so the inclu- sion of autonegotiation ensures that the highest-perfor- mance protocol will be selected based on the ability of the link partner. the autonegotiation function within the LU3X31T-T64 can be controlled either by internal register access or by the use of configuration pins. at powerup and at device reset, the configuration pins are sampled. if dis- abled, autonegotiation will not occur until software enables bit 12 in register 0. if autonegotiation is enabled, the negotiation process will commence imme- diately. when autonegotiation is enabled, the LU3X31T-T64 transmits the abilities programmed into the autonegoti- ation advertisement register at address 04h via flp bursts. any combination of 10 mbits/s, 100 mbits/s, half-duplex, and full-duplex modes may be selected. autonegotiation controls the exchange of configuration information. upon successful autonegotiation, the abili- ties reported by the link partner are stored in the auto- negotiation link partner ability register at address 05h. the contents of the autonegotiation link partner ability register are used to automatically configure to the highest-performance protocol between the local and far-end nodes. software can determine which mode has been configured by autonegotiation by comparing the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of high- est priority relative to the following list: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register (bmcr) at address 00h provides control of enabling, disabling, and restart- ing of the autonegotiation function. when autonegotia- tion is disabled, the speed selection bit (bit 13) controls switching between 10 mbits/s or 100 mbits/s operation, while the duplex mode bit (bit 8) controls switching between full-duplex operation and half-duplex opera- tion. the speed selection and duplex mode bits have no effect on the mode of operation when the autonego- tiation enable bit (bit 12) is set. the basic mode status register (bsmr) at address 01h indicates the set of available abilities for technology types (bits 15 to 11), autonegotiation ability (bit 3), and extended register capability (bit 0). these bits are hard- wired to indicate the full functionality of the lu3x31t- t64. the bmsr also provides status on: 1. whether autonegotiation is complete (bit 5). 2. whether the link partner is advertising that a remote fault has occurred (bit 4). 3. whether a valid link has been established (bit 2). the autonegotiation advertisement register at address 04h indicates the autonegotiation abilities to be adver- tised by the LU3X31T-T64. all available abilities are transmitted by default, but any ability can be sup- pressed by writing to this register or configuring exter- nal pins.
lucent technologies inc. 19 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx functional description (continued) the autonegotiation link partner ability register at address 05h indicates the abilities of the link partner as indicated by autonegotiation communication. the con- tents of this register are considered valid when the autonegotiation complete bit (bit 5, register address 01h) is set. reset operation the LU3X31T-T64 can be reset either by hardware or software. a hardware reset is accomplished by applying a negative pulse, with a duration of at least 1 ms, to the rstz pin of the LU3X31T-T64 during normal operation. a software reset is activated by setting the reset bit in the basic mode control register (bit 15, register 00h). this bit is self-clearing and, when set, will return a value of 1 until the software reset operation has com- pleted. both hardware and software reset operations initialize all registers to their default values. this process includes re-evaluation of all hardware-configurable registers. logic levels on several i/o pins are detected during hardware reset period to determine the initial function- ality of LU3X31T-T64. some of these pins are used as outputs after the reset operation. care must be taken to ensure that the configuration setup will not interfere with normal operation. dedi- cated configuration pins can be tied to v cc or ground directly. configuration pins multiplexed with logic-level output functions should be either weakly pulled up or weakly pulled down through resisters. configuration pins multiplexed with led outputs should be set up with one of the following circuits shown in figure 5. note: the 10 k w resistor is only for nondefault configuration. 5-6783(f).r2 figure 5. hardware reset configurations phy address during hardware reset, the logic levels of pins 10, 12, 16, 34, and 39 are latched into bits 4 through 0 of manage- ment register at address 19h, respectively. this 5-bit address is used as the phy address for serial management interface communication. note that initializing the phy address to zero automatically isolates the mii interface. autonegotiation and speed configuration the five pins listed in table 11 configure the speed capability of LU3X31T-T64. the logic state of these pins, at powerup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose. these pins are also used for evaluating the default value in the base mode control register (register 00h) according to table 11. v cc i/o pin i/o pin logic 1 configuration logic 0 configuration 10 k w 10 k w
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 20 lucent technologies inc. functional description (continued) table 11. autonegotiation 100base-x pcs configuration the logic state of bpscr, bp4b5b, and bpalign pins latched into bits 15, 14, and 12 of the config 100 register at address 18h during powerup or reset. these registers configure the functionality of 100base-x pcs (physical cod- ing sublayer) mii registers. table 12. mii management registers configuration pins at reset registers initial value autoen pin 4 100fden pin 2 (reg 4.8) 100hden pin 11 (reg 4.7) 10fden pin 17 (reg 4.6) 10hden pin 43 (reg 4.5) autonegotiate reg 0.12 speed reg 0.13 duplex reg 0.8 0 1xxx 0 1 1 0011x 0 1 1 0010x 0 1 0 0001x 0 0 1 00001 0 0 0 1xxxx 1 0 0 address register name basic/extended 0h control register b 1h status register b 2h ? 3h phy identifier register e 4h autonegotiation advertisement register e 5h autonegotiation link partner ability register e 6h autonegotiation expansion register e 7h ? fh ieee reserved e 15h receive error counter e 17h phy control/status register e 18h config 100 register e 19h phy address register e 1ah config 10 register e 1bh status 100 register e 1ch status 10 register e 1dh interrupt mask register e 1eh interrupt status register e
lucent technologies inc. 21 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers legend: ro read only. r/w read and write capable. sc self-clearing. ll latching low, unlatch on read. lh latching high, unlatch on read. cor clear on read. table 13. control register (register 0h) bit(s) name description r/w default 15 reset 1 ? phy reset. 0 ? normal operation. setting this bit initiates the software reset function that resets the entire LU3X31T-T64 device, except for the phase-locked loop cir- cuit. it will relatch in all hardware configura- tion pin values and set all registers to their default values. the software reset process takes 25 m s to complete. this bit, which is self-clearing, returns a value of 1 until the reset process is complete. r/w sc 0h 14 loopback 1 ? enable loopback mode. 0 ? disable loopback mode. this bit controls the phy loopback operation that isolates the network transmitter outputs (tptx ) and routes the mii transmit data to the mii receive data path. this function should only be used when autonegotiation is disabled (bit 12 = 0). the specific phy (10base-t or 100base-x) used for this oper- ation is determined by bits 12 and 13 of this register. r/w 0h 13 speed selection 1 ? 100 mbits/s. 0 ? 10 mbits/s. link speed is selected by this bit or by auto- negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored). at powerup or reset, this bit will be set unless autonen, 100fden, and 100hden pin are all in logic low state. r/w pin 12 autonegotiation enable 1 ? enable autonegotiation process. 0 ? disable autonegotiation process. this bit determines whether the link speed should be set up by the autonegotiation pro- cess. it is set at powerup or reset if the autonen pin (pin 4) detects a logic 1 input level. r/w pin
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 22 lucent technologies inc. 11 powerdown 1 ? powerdown. 0 ? normal operation. setting this bit puts the LU3X31T-T64 into powerdown mode. during the powerdown mode, tptx and all led outputs are 3- stated, and the mii interface is isolated. rstz is used to clear this bit. r/w 0h 10 isolate 1 ? isolate phy from mii. 0 ? normal operation. setting this control bit isolates the LU3X31T-T64 from the mii, with the excep- tion of the serial management interface. when this bit is asserted, the LU3X31T-T64 does not respond to txd[3:0], txen, and txer inputs, and it presents a high imped- ance on its txclk, rxclk, rxdv, rxer, rxd[3:0], col, and crs outputs. this bit is initialized to 0 unless the configuration pins for the phy address are set to 00000h during powerup or reset. r/w pin 9 restart autonegotiation 1 ? restart autonegotiation process. 0 ? normal operation. setting this bit while autonegotiation is enabled forces a new autonegotiation pro- cess to start. this bit is self-clearing and returns to 0 after the autonegotiation process is completed. r/w, sc 0h 8 duplex mode 1 ? full-duplex mode. 0 ? half-duplex mode. if autonegotiation is disabled, this bit deter- mines the duplex mode for the link. at powerup or reset, this bit is set to 1 if the autonen pin (pin 4) detects a logic 0 and either 100fden (pin 2) or 10fden pin (pin 17) detects a logic 1. r/w pin 7 collision test 1 ? enable col signal test. 0 ? disable col signal test. when set, this bit will cause the col signal to be asserted in response to the assertion of txen. r/w 0h 6:0 reserved not used. ro 0h bit(s) name description r/w default mii registers (continued) table 13. control register (register 0h) (continued)
lucent technologies inc. 23 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers (continued) table 14. status register (register 1h) bit(s) name description r/w default 15 100base-t4 1 ? capable of 100base-t4. 0 ? not capable of 100base-t4. this bit is hardwired to 0, indicating that the LU3X31T-T64 does not support 100base-t4. ro 0h 14 100base-x full-duplex 1 ? capable of 100base-x full-duplex mode. 0 ? not capable of 100base-x full-duplex mode. this bit is hardwired to 1, indicating that the LU3X31T-T64 supports 100base-x full- duplex mode. ro 1h 13 100base-x half-duplex 1 ? capable of 100base-x half-duplex mode. 0 ? not capable of 100base-x half-duplex mode. this bit is hardwired to 1, indicating that the LU3X31T-T64 supports 100base-x half- duplex mode. ro 1h 12 10 mbits/s full-duplex 1 ? capable of 10 mbits/s full-duplex mode. 0 ? not capable of 10 mbits/s full-duplex mode. this bit is hardwired to 1, indicating that the LU3X31T-T64 supports 10base-t full-duplex mode. ro 1h 11 10 mbits/s half-duplex 1 ? capable of 10 mbits/s half-duplex mode. 0 ? not capable of 10 mbits/s half-duplex mode. this bit is hardwired to 1, indicating that the LU3X31T-T64 supports 10base-t half-duplex mode. ro 1h 10 100base-t2 1 ? capable of 100base-t2. 0 ? not capable of 100base-t2. this bit is hardwired to 0, indicating that the LU3X31T-T64 does not support 100base-t2. ro 0h 9:7 reserved ignore when read. ro 0h 6 mf preamble suppression 1 ? accepts management frames with pre- amble suppressed. 0 ? will not accept management frames with preamble suppressed. this bit is hardwired to 1, indicating that the LU3X31T-T64 accepts management frame without preamble. a minimum of 32 pre- amble bits are required following power-on or hardware reset. one idle bit is required between any two management transactions as per ieee 802.3u specification. ro 1h
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 24 lucent technologies inc. 5 autonegotiation complete 1 ? autonegotiation process completed. 0 ? autonegotiation process not completed. if autonegotiation is enabled, this bit indicates whether the autonegotiation process has been completed. ro 0h 4 remote fault 1 ? remote fault detected. 0 ? remote fault not detected. this bit is latched to 1 if the rf bit in the auto- negotiation link partner ability register (bit 13, register address 05h) is set or the receive channel meets the far-end fault indication function criteria. it is unlatched when this reg- ister is read. ro, lh 0h 3 autonegotiation ability 1 ? capable of autonegotiation. 0 ? not capable of autonegotiation. this bit defaults to 1, indicating that the LU3X31T-T64 is capable of autonegotiation. ro 1h 2link status1 ? link is up. 0 ? link is down. this bit reflects the current state of the link- test-fail state machine. loss of a valid link causes a 0 latched into this bit. it remains 0 until this register is read by the serial man- agement interface. ro, ll 0h 1jabber detect1 ? jabber condition detected. 0 ? jabber condition not detected. during 10base-t operation, this bit indicates the occurrence of a jabber condition. it is implemented with a latching function so that it becomes set until it is cleared by a read. ro, lh 0h 0 extended capability 1 ? extended register set. 0 ? no extended register set. this bit defaults to 1, indicating that the LU3X31T-T64 implements extended regis- ters. ro 1h bit(s) name description r/w default mii registers (continued) table 14. status register (register 1h) (continued)
lucent technologies inc. 25 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers (continued) table 15. phy identifier (register 2h) table 16. phy identifier (register 3h) table 17. autonegotiation advertisement (register 4h) table 18. autonegotiation link partner ability (register 5h) bit(s) name description r/w default 15:0 phy-id[31:16] ieee address. ro 0043h bit(s) name description r/w default 15:10 phy-id[15:10] ieee address. ro 011101b 9:4 phy-id[9:4] model no. ro 000001b 3:0 phy-id[3:0] rev. no. ro 0001b bit(s) name description r/w default 15 next page 1 ? capable of next-page function. 0 ? not capable of next-page function. this bit defaults to 0, indicating that LU3X31T-T64 is not next-page capable. ro 0h 14 reserved reserved. ro 0h 13 remote fault 1 ? remote fault has been detected. 0 ? no remote fault has been detected. this bit is written by serial management interface for the purpose of communicat- ing the remote fault condition to the auto- negotiation link partner. r/w 0h 12:10 ieee reserved these 3 bits default to 0. ro 0h 9 technology ability field for 100base-t4 this bit defaults to 0, indicating that the LU3X31T-T64 does not support 100base-t4. ro 0h 8:5 technology ability field this 4-bit field contains the advertised ability of this phy. at powerup or reset, the logic level of 100fden, 100hden, 10fden, and 10hden pins are latched into bits 8 through 5, respectively. r/w pin 4:0 selector field these 5 bits are hardwired to 00001h, indicating that the LU3X31T-T64 supports ieee 802.3 csma/cd. ro 01h bit(s) name description r/w default 15 next page 1 ? capable of next-page function. 0 ? not capable of next-page function. ro 0h 14 acknowledge 1 ? link partner acknowledges reception of the ability data word. 0 ? not acknowledged. ro 0h 13 remote fault 1 ? remote fault has been detected. 0 ? no remote fault has been detected. ro 0h 12:5 technology ability field supported technologies. ro 0h 4:0 selector field encoding definitions. ro 0h
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 26 lucent technologies inc. mii registers (continued) table 19. autonegotiation expansion register (register 6h) table 20. receive error counter (register 15h) bit(s) name description r/w default 15:5 reserved reserved. ro 0h 4 parallel detection fault 1 ? fault has been detected. 0 ? no fault detected. this bit is set if the parallel detection fault state of the autonegotiation arbitration state machine is visited during the auto- negotiation process. it will remain set until this register is read. ro, lh 0h 3 link partner next-page able 1 ? link partner is next-page capable. 0 ? link partner is not next-page capable. this bit indicates whether the link partner is next-page capable. it is meaningful only when the autonegotiation complete bit (bit 5, register 1) is set. ro 0h 2 next-page able 1 ? local device is next-page capable. 0 ? local device is not next-page capa- ble. this bit defaults to 0, indicating that the LU3X31T-T64 is not next-page able. ro 0h 1 page received 1 ? a new page has been received. 0 ? no new page has been received. this bit is latched to 1 when a new link code word page has been received. this bit is automatically cleared when the autonegotiation link partner ability regis- ter (register 05h) is read by management interface. ro, lh 0h 0 link partner autonegotiatable 1 ? link partner is autonegotiable. 0 ? link partner is not autonegotiable. ro 0h bit(s) name description r/w default 15:0 rx error count number of receive errors since last reset. the counter is incremented once for each packet that has receive error condition detected. this counter may roll over depending on value of the csmode bit (bit 13 of register 17h). ro, cor 0h
lucent technologies inc. 27 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers (continued) table 21. phy control/status register (register 17h) bit(s) name description r/w default 15:14 reserved reserved. ro 0h 13 csmode 1 ? counter sticks at ffffh. 0 ? counters roll over. this bit controls the operation of isolate counter, false carrier counter, and receive error counters. r/w 0h 12 tptxtr 1 ? 3-state transmit pairs. 0 ? normal operation. when this bit is set, the twisted-pair trans- mitter outputs are 3-stated. note that the twisted-pair transmit driver can be 3- stated by either this bit or the tptxtr pin (pin 5). r/w 0h 11 thunderlan interrupt enable 1 ? mdio thunderlan interrupt enabled. 0 ? mdio thunderlan interrupt disabled. this bit enables/disables the ti thunder- lan interrupt mechanism. r/w 0h 10 mf preamble suppression enable 1 ? mdio preamble suppression enabled. 0 ? mdio preamble suppression disabled. LU3X31T-T64 can accept management frames without preamble as described in bit 6 of register 1h. this bit allows the user to enable or disable the preamble sup- pression function. r/w 0h 9 speed status 1 ? part is in 100 mbits/s mode. 0 ? part is in 10 mbits/s mode. this value is not defined during the auto- negotiation period. ro 0h 8 duplex status 1 ? part is in full-duplex mode. 0 ? part is in half-duplex mode. this value is not defined during the auto- negotiation period. ro 0h 7 activity led on 1 ? ledtx/actled active on both trans- mit and receive. 0 ? ledtx/actled active on transmit only. r/w 0h 6 ledrx off 1 ? 3-state ledrx output. 0 ? normal operation. r/w 0 5ledtx/actled off1 ? 3-state ledtx/actled output. 0 ? normal operation. r/w 0 4 lnkled off 1 ? 3-state lnkled output. 0 ? normal operation. r/w 0 3 ledcol off 1 ? 3-state ledcol output. 0 ? normal operation. r/w 0 2ledfd off1 ? 3-state ledfd output. 0 ? normal operation. r/w 0 1ledsp off1 ? 3-state ledsp output. 0 ? normal operation. r/w 0
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 28 lucent technologies inc. table 22. config 100 register (register 18h) 0 led pulse stretching disable 1 ? led pulse stretching disabled. 0 ? led pulse stretching enabled. when pulse stretching is enabled, all led outputs are stretched to 48 ms72 ms. r/w 0 bit(s) name description r/w default 15 bpscr 1 ? disable scrambler/descrambler. 0 ? enable scrambler/descrambler. this bit is initialized to the logic level of bpscr pin (pin 41) at powerup or reset. r/w pin 14 bp4b5b 1 ? disable 4b/5b encoder/decoder. 0 ? enable 4b/5b encoder/decoder. this bit is initialized to the logic level of bp4b5b pin (pin 42) at powerup or reset. r/w pin 13 reserved reserved. ro 0h 12 bpalign 1 ? pass unaligned data to mii. 0 ? pass aligned data to mii. this bit is initialized to the logic level of bpalign pin (pin 44) at powerup or reset. r/w pin 11:10 reserved reserved. ro 0h 9 force good link 100 1 ? force good link in 100 mbits/s mode. 0 ? normal operation. r/w 0h 8:6 reserved reserved. ro 0h 5accept halt1 ? passes halt symbols to the mii. 0 ? normal operation. r/w 0h 4 load seed 1 ? loads the scrambler seed. 0 ? normal operation. setting this bit loads the user seed stored in register 19h into the 100base-x scram- bler. the content of this bit returns to 0 after the loading process is completed and no transmit is active. r/w, sc 0h 3 burst mode 1 ? burst mode. 0 ? normal operation. setting this bit expands the 722 m s scram- bler time-out period to 2,000 m s. r/w 0h 2:0 reserved reserved. ro 0h bit(s) name description r/w default mii registers (continued) table 21. phy control/status register (register 17h) (continued)
lucent technologies inc. 29 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers (continued) table 23. phy address register (register 19h) table 24. config 10 register (register 1ah) bit(s) name description r/w default 15:11 reserved reserved. ro 0h 10:5 user seed user-modifiable seed data. when the load seed bit (bit 4 of register 18h) is set, bits 15 through 5 of this register are loaded into the 100base-x scrambler. r/w 21h 4:0 phy address these 5 bits store the part address used by the serial management interface. phy address of 0 has the special function of isolating the part from the mii. these bits are initialized to the logic levels of phy[4:0] pins at powerup or reset. r/w pin bit(s) name description r/w default 15 reserved reserved. ro 0h 14 force 10 mbits/s good link 1 ? force 10 mbits/s good link. 0 ? normal operation. r/w 0h 13 reserved reserved. ro 0h 12 sqe disable 1 ? signal quality error test disabled. 0 ? normal operation. r/w 0h 11 low squelch select 1 ? low squelch level selected. 0 ? normal squelch level selected. r/w 0h 10 jabber disable 1 ? jabber function disabled. 0 ? normal operation. r/w 0h 9:7 reserved reserved. ro 0h 6 powerdown mode 1powers down the LU3X31T-T64 com- pletely. the part comes out of this mode after a reset is asserted and deasserted. 0normal operation. r/w 0h 5:4 reserved reserved. ro 0h 3 autopolarity disable 1disable autopolarity function. 0enable autopolarity function. r/w 0h 2:0 reserved reserved. ro 0h
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 30 lucent technologies inc. mii registers (continued) table 25. status 100 register (register 1bh) table 26. status 10 register (register 1ch) table 27. interrupt mask register (register 1dh) bit(s) name description r/w default 15:14 reserved reserved. ro 0h 13 pll lock status 1 ? 100 mbits/s pll locked. 0 ? 100 mbits/s pll not locked. ro 0h 12:0 reserved reserved. ro 0h bit(s) name description r/w default 15 polarity 1 ? polarity of cable is swapped. 0 ? polarity of cable is correct. ro 0h 14:0 reserved reserved. ro 0h bit(s) name description r/w default 15 reserved reserved. ro 0h 14 receiver error counter full 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 13 reserved reserved. ro 0h 12 remote fault 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 11 autoneg. complete 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 10 link up 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 9 link down 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 8 data recovery 100 lock up 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 7 data recovery lock down 0 ? enable interrupt. 1 ? disable interrupt. r/w 0h 6:0 reserved reserved. ro 0h
lucent technologies inc. 31 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx mii registers (continued) table 28. interrupt status register (register 1eh) dc and ac specifications absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 29. absolute maximum ratings table 30. operating conditions bit(s) name description r/w default 15 reserved reserved. ro 0h 14 receiver error counter full 1 ? receive error counter has rolled over. 0 ? receive error counter has not rolled over. ro, lh 0h 13 reserved reserved. ro 0h 12 remote fault 1 ? remote fault observed by phy. 0 ? remote fault not observed by phy. ro, lh 0h 11 autonegotiation com- plete 1 ? autonegotiation has completed. 0 ? autonegotiation has not completed. ro, lh 0h 10 link up 1 ? link is up. 0 ? no change on link status. ro, lh 0h 9 link down 1 ? link has gone down. 0 ? no change on link status. ro, lh 0h 8 data recovery 100 lock up 1 ? data recovery has locked. 0 ? data recovery is not locked. ro, lh 0h 7 data recovery 100 lock down 1 ? data recovery is not locked. 0 ? data recovery has locked. ro, lh 0h 6:0 reserved reserved. ro 0h parameter symbol min max unit ambient operating temperature t a 070 c storage temperature t stg C65 150 c maximum supply voltage 3.46 v voltage on mii input pins with respect to ground C0.5 5.25 v voltage on any other pin with respect to ground C0.5 3.46 v parameter symbol min typ max unit operating supply voltage 3.135 3.3 3.46 v power dissipation * : 100 mbits/s tx 10 mbits/s autonegotiating * power dissipations are specified at 3.3 v and 25 c. this is the power dissipated by the LU3X31T-T64. p d p d p d 140 150 30 ma ma ma
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 32 lucent technologies inc. dc and ac specifications (continued) table 31. dc characteristics clock timing table 32. system clock (xin) 5-6784(f) figure 6. system timing parameter symbol conditions min max unit recommended power supply v dd v ss 3.0 0.0 3.6 0.0 v v supply current 100base-tx i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 148ma supply current 10base-tx i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 156ma supply current autonegotiation mode i dd v dd = 3.3 v, v ss = 0.0 v no link 70ma supply current 100base-fx i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 120ma ttl input high voltage v ih v dd = 3.3 v, v ss = 0.0 v 2.0 v ttl input low voltage v il v dd = 3.3 v, v ss = 0.0 v 0.8 v ttl output high-voltage mii pins v oh v dd = 3.3 v, v ss = 0.0 v i oh = 4 ma 2.4 v ttl output low-voltage mii pins v ol v dd = 3.3 v, v ss = 0.0 v i oh = 4 ma 0.4v ttl output high-voltage led pins v oh2 v dd = 3.3 v, v ss = 0.0 v i oh = 10 ma 3.0 v ttl output low-voltage led pins v ol2 v dd = 3.3 v, v ss = 0.0 v i oh = 10 ma 0.3v pecl input high voltage v ihpecl v dd C 1.16 v dd C 0.88 v pecl input low voltage v ilpecl v dd C 1.81 v dd C 1.47 v pecl output high voltage v ohpecl v dd C 1.02 v pecl output low voltage v olpecl v dd C 1.62 v oscillator input (25 mhz) x in C50 50 ppm crystal freq. stability (25 mhz) x in /x out C50 50 ppm input capacitance mii c in 8pf symbol description min max unit t1 clock high pulse width 17 23 ns t2 clock low pulse width 17 23 ns t3 clock period 39.998 40.002 ns x in t2 t1 t3
lucent technologies inc. 33 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx clock timing (continued) table 33. transmit clock (input and output) * specified at 100 ppm. 5-6785(f) figure 7. transmit timing (input and output) symbol description min max unit t1 txclk high pulse width (100 mbits/s) 14 26 ns txclk high pulse width (10 mbits/s) 140 260 ns t2 x in rise to txclk rise (100 mbits/s) 14 ns x in rise to txclk rise (10 mbits/s) 28 ns t3 txclk low pulse width (100 mbits/s) 14 26 ns txclk low pulse width (10 mbits/s) 140 260 ns t4 txclk period (100 mbits/s)* 40 40 ns txclk period (10 mbits/s)* 400 400 ns x in t2 t3 t1 t4 txclk
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 34 lucent technologies inc. clock timing (continued) table 34. management clock 5-6786(f) figure 8. management timing symbol description min max unit t1 mdc high pulse width 200 ns t2 mdc low pulse width 200 ns t3 mdc period 400 ns t4 mdio(i) setup to mdc rising edge 10 ns t5 mdio(o) hold time from mdc rising edge 10 ns t6 mdio(o) valid from mdc rising edge 0 300 ns mdc t2 t1 mdio(i) mdio(o) t4 t5 t6 t3
lucent technologies inc. 35 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx clock timing (continued) table 35. mii receive timing 5-6787(f).c figure 9. mii receive timing symbol description min max unit t1 rxer, rxdv, rxd[3:0] setup to rxclk rise 10 ns t2 rxer, rxdv, rxd[3:0] hold after rxclk rise 10 ns t3 rxclk high pulse width (100 mbits/s) 14 26 ns rxclk high pulse width (10 mbits/s mii) 140 260 ns rxclk high pulse width (10 mbits/s serial) 35 65 ns t4 rxclk low pulse width (100 mbits/s) 14 26 ns rxclk low pulse width (10 mbits/s mii) 140 260 ns rxclk low pulse width (10 mbits/s serial) 35 65 ns t5 rxclk period (100 mbits/s) 40 40 ns rxclk period (10 mbits/s mii) 400 400 ns rxclk period (10 mbits/s serial) 100 100 ns rxclk t1 rxer, rxdv, rxd[3:0] t4 t5 t3 t2
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 36 lucent technologies inc. clock timing (continued) table 36. mii transmit timing 5-6788(f) figure 10. mii transmit timing symbol description min max unit t1 txer, txen, txd[3:0] setup to txclk rise 10 ns t2 txer, txen, txd[3:0] hold after txclk rise 0 25 ns t2 t1 txclk txer, txen, txd[3:0]
lucent technologies inc. 37 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx clock timing (continued) table 37. transmit timing 5-6789(f) figure 11. transmit timing symbol description min max unit t1 txen sampled to crs high (100 mbits/s) 0 4 bits txen sampled to crs high (10 mbits/s) 1.5 bits t2 txen sampled to crs low (100 mbits/s) 0 16 bits txen sampled to crs low (10 mbits/s) 16 bits t3 transmit latency (100 mbits/s) 6 14 bits transmit latency (10 mbits/s) 4 bits t4 sampled txen inactive to end of frame (100 mbits/s) 17bits sampled txen inactive to end of frame (10 mbits/s) 5bits txclk t1 crs txen tptx preamble t3 t2 t4
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 38 lucent technologies inc. clock timing (continued) table 38. receive timing 5-6790(f) figure 12. receive timing symbol description min max unit t1 receive frame to sampled edge of rxdv (100 mbits/s) 15bits receive frame to sampled edge of rxdv (10 mbits/s) 22bits t2 receive frame to crs high (100 mbits/s) 13 bits receive frame to crs high (10 mbits/s) 5 bits t3 end of receive frame to sampled edge of rxdv (100 mbits/s) 12bits end receive frame to sampled edge of rxdv (10 mbits/s) 4bits t4 end of receive frame to crs low (100 mbits/s) 13 24 bits end of receive frame to crs low (10 mbits/s) 4.5 bits rxclk crs rxdv tprx t1 t2 t3 t4 data
lucent technologies inc. 39 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx clock timing (continued) table 39. reset and configuration timing 5-6791(f) figure 13. reset and configuration timing symbol description min max unit t1 power on to reset high 1.0 ms t2 reset pulse width 1.0 ms t3 configuration pin setup 1.0 ms t4 configuration pin hold 1.0 ms v cc rstz config t3 t4 t2 t1
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 40 lucent technologies inc. clock timing (continued) table 40. pmd characteristics 5-6792(f).a figure 14. pmd timing symbol description min max unit t1 tptx+/tptxC rise time 3.0 5.0 ns t2 tptx+/tptxC fall time 3.0 5.0 ns t3 tp skew 0 500 ps t3 t2 t1 tptx+ tptxC
lucent technologies inc. 41 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx clock timing (continued) 5-6793(f).cr.1 figure 15. connection diagrams (frequency references) x in x out 25 mh z 50 ppm 20 pf 20 pf x in x out gnd 25 mh z osc 50 ppm 25 mh z crystal reference 25 mh z oscillator reference
LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 42 lucent technologies inc. clock timing (continued) 5-6794(f).c figure 16. connection diagrams (10/100btx operation) digital v dd transmit v dd receive v dd tptx+ tptxC tprx+ tprxC ref100 ref10 receive gnd transmit gnd digital gnd LU3X31T-T64 transmit receive magnetic rj45 tx+ txC rx+ unused unused rxC unused unused gnd 301 w 4.64 k w 0.1 m f fb fb gnd v cc 0.1 m f 22 m f gnd 0.1 m f 0.1 m f 50 w 50 w 54 w 54 w chassis gnd 470 pf 3 kv 75 w 75 w 75 w 75 w 0.1 m f 1000 pf csvcc 4.7 m f 1 w gnd v cc
lucent technologies inc. 43 preliminary data sheet LU3X31T-T64 single-port 3 v july 2000 10/100 ethernet transceiver tx outline diagram 64-pin tqfp dimensions are in millimeters. 5-7101(f) detail a 0.50 typ 1.60 max seating plane 0.08 detail b 0.05/0.15 1.40 0.05 10.00 0.20 12.00 0.20 1 64 49 16 17 32 48 33 10.00 0.20 12.00 0.20 pin #1 identifier zone detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 detail b 0.19/0.27 0.08 m 0.106/0.200
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved july 2000 ds00-358lan (replaces ds99-346lan) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) LU3X31T-T64 single-port 3 v preliminary data sheet 10/100 ethernet transceiver tx july 2000 ordering information device code package temperature comcode LU3X31T-T64 64-pin tqfp 0 c to 70 c 108497249

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